FOUR LAYERS. ONE CONNECTED PROCESS.Preparing your design files
THE FOUR-LAYER WORKBENCH

PCB Microstrip Impedance Estimator

Compare a limited microstrip scenario before discussing the real stackup. The calculator models a zero-thickness trace over a continuous reference plane.

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Use the model only for its intended structure

Microstrip places a signal conductor above a reference plane with dielectric between them and air above. This calculator is for a single-ended, zero-thickness conductor. It does not model differential coupling, stripline, coplanar ground, solder mask, surface roughness or frequency-dependent material behavior.

The permitted width-to-height ratio is 1 to 10, and relative permittivity is restricted to 1 through 12. Those are deliberately limited operating bounds for this planning implementation; they are not a statement of production capability.

L1Signal + components
Prepreg dielectric
L2Ground reference
Core dielectric
L3Power or ground
Prepreg dielectric
L4Signal + components
Illustrative four-layer construction. Layer assignments and dielectric dimensions are confirmed for each design.

Understand the inputs

Width is the nominal trace width and height is the dielectric distance from the trace to its reference plane. Both use millimeters. Relative permittivity is dimensionless. Use a material property appropriate to the intended analysis rather than assuming every FR4 laminate has one fixed value.

Because the calculation uses a width-to-height ratio, changing both dimensions by the same factor leaves the idealized estimate unchanged. Real conductor thickness and manufacturing effects do not necessarily scale in the same way.

Check a worked example

For a trace width of 0.4 mm, dielectric height of 0.2 mm and relative permittivity of 4, the width-to-height ratio is 2. The effective dielectric constant is approximately 3.067 and the idealized characteristic impedance is approximately 51.0 Ω. This is a mathematical example, not a production geometry recommendation.

The quasi-static expression estimates effective permittivity as (εr + 1) / 2 + (εr − 1) / (2√(1 + 12h/w)). It then estimates impedance as 120π divided by √εeff × [w/h + 1.393 + 0.667 ln(w/h + 1.444)]. The implementation uses the wide-trace branch within its stated bounds.

Move from an estimate to a controlled requirement

A controlled-impedance release identifies the target, tolerance, signal layer, reference layer, trace structure and validation method. The fabricator may need to adjust trace geometry to the available construction. Review those changes against the design before release.

For background on the idealized equations, see the University of Houston microstrip design reference. Use a suitable field solver and the agreed material construction for final design work.

Microstrip impedance estimate

Change the dimensions to compare a planning scenario. All inputs are illustrative defaults. Input ranges describe this calculator, not manufacturing capabilities.

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Planning aid only. Results are not a manufacturing approval, guaranteed tolerance or production quotation.

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