Decide which nets actually need control
Use the component and interface documentation to identify the required signaling structure. Fast edge rates can make interconnect behavior relevant even when the repetition rate looks modest. Conversely, a board should not receive an unexplained blanket impedance requirement merely because it contains a digital device. Name the nets or net classes and record their design basis.
The Texas Instruments high-speed layout guide emphasizes rise time and return paths alongside routing geometry. For your project, preserve the device-specific rules, connector transitions and termination assumptions in the review package. These establish what the board-level impedance target is intended to support.
Separate single-ended and differential definitions
A single-ended target describes a conductor relative to its reference environment. A differential target describes a pair in its coupled structure. Pair spacing therefore joins trace width, copper thickness, dielectric properties and reference-plane spacing as an important input. A differential requirement should not be reduced to two independently selected single-ended widths.
Identify whether a structure is on an external or internal layer and which plane provides its reference. Include nearby copper and solder-mask assumptions when they affect the model. If the design changes layer, review the transition and the return connection. A well-defined uniform trace section does not automatically resolve discontinuities at vias, pads or connectors.
| Input | Single-ended structure | Differential structure |
|---|---|---|
| Target | Impedance and tolerance | Differential impedance and tolerance |
| Geometry | Width and finished copper | Width, pair gap and finished copper |
| Reference | Plane and dielectric spacing | Plane, spacing and coupled environment |
| Coverage | Named nets and layers | Named pair classes and layers |
| Verification | Agreed coupon and method | Representative pair coupon and method |
Approve the stackup before locking the final widths
An early calculation is useful for comparing arrangements. Its result depends on the assumptions entered, and it does not establish that a corresponding material construction is available. Send the target structure and ask for a proposed stackup with modeled trace geometry. Check whether the proposed widths fit the escape routing and connector footprints.
Agree what adjustments are permissible. Engineering may need to change trace geometry to meet the target within the proposed process. That permission should specify affected nets and any routing constraints, rather than giving unrestricted authority to alter artwork. If a change conflicts with component spacing or differential-pair rules, return the design for a coordinated revision.
Protect the reference along the complete route
Trace geometry is only part of the route. Inspect reference-plane continuity, transitions between layers and the path near connector breakouts. A route that crosses an unintended void has a different local environment from the uniform structure used to calculate its nominal impedance. Identify these regions in layout review instead of expecting a fabrication tolerance to correct them.
For mixed power and signal arrangements, explicitly map which reference is available under each critical route. Do not assume that every four-layer allocation provides equivalent routing freedom. Where constraints cannot be reconciled, consider a different placement, routing layer or layer count. The decision should follow the interface and layout needs rather than a universal preferred stackup.
Define what a measurement report represents
Agree the target, tolerance, coupon structure and measurement method before manufacturing release. A coupon is intended to represent the relevant construction; it is not a measurement of every discontinuity on every product net. Ask which layer structures are covered and how the results identify the revision and lot.
Separate coupon acceptance from system validation. A board may satisfy its agreed impedance verification while an assembled link still encounters connector, termination, timing or power-integrity issues. Conversely, a working prototype does not replace a production requirement if geometry control is part of the release specification. Treat manufacturing evidence and product-level performance tests as distinct parts of the plan.
Send an impedance requirement table with the files
For each net class, list the signal layers, reference layers, target, acceptance range and relevant geometry. Attach the stackup version and indicate whether dimensions are fixed or may be tuned during review. Call out special transitions and retain the component documentation that establishes the target.
Use the impedance estimator only within its stated model limits. Explore four-layer stackups and electrical testing to distinguish geometry verification from connectivity checks. The capability directory provides adjacent requirements. Submit your impedance table through Request a Quote for engineering confirmation of the actual construction and verification scope.
Impedance specification readiness
Use this checklist to prepare your inquiry. These selections stay in this browser and do not submit a project.
Frequently asked questions
Does specifying controlled impedance choose my stackup automatically?
No. The target must be reconciled with material, copper, thickness and routing constraints. Review and approve the proposed construction and geometry before assuming your layout is ready for fabrication.
Can a simple calculator replace engineering analysis?
A calculator can support early decisions within its model assumptions. It cannot establish material availability or capture every three-dimensional transition, process detail or surrounding conductor in a real board.
Is differential impedance always twice the single-ended value?
No. Coupling between the two traces affects the differential structure. Use a model appropriate to the pair geometry and reference environment rather than applying an unconditional multiplier.
Does a coupon verify every trace on the board?
No. It provides evidence for an agreed representative structure and test method. Layout discontinuities and assembled interface performance require separate design review and validation.
Can trace widths be changed during engineering review?
Only within the agreed approval process. Identify which dimensions may be tuned, preserve footprint and spacing constraints, and record the accepted change against the released artwork revision.